1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a data input circuit of a semiconductor memory apparatus and a data input method using the same.
2. Related Art
In general, a conventional semiconductor memory apparatus aligns a plurality of data bits, which are input in series, in parallel to each other by using a data input strobe signal, amplifies the data, and transmits the data to global Input/Output lines GIO. At this time, starting addresses determine global Input/Output lines to which data is transmitted among a plurality of global Input/Output lines. The starting addresses indicate some of the plurality-bit column addresses, and are used to select the global Input/Output lines.
A data input circuit included in a conventional semiconductor memory apparatus activates a plurality of data input sense amplifiers using a data input strobe signal and starting addresses. Each of the activated data input sense amplifiers amplifies data, which is allocated by the starting addresses among a plurality of data, and transmits the amplified data to a corresponding data input driver. Each of the plurality of data input drivers loads data transmitted by the corresponding data input sense amplifier to a corresponding global Input/Output line.
Since the general data input circuit uses a large number of signals, a large number of signal lines need to be provided in the data input circuit. As a result, the data input circuit occupies a large area.
FIG. 1 is a block diagram illustrating the structure of a data input circuit of a conventional semiconductor memory apparatus. In this case, a burst length is 4. Therefore, four data components are transmitted to four global Input/Output lines.
As shown in FIG. 1, the conventional data input circuit includes a data input strobing unit 10, first to fourth data input sense amplifiers 21 to 24, and first to fourth data input drivers 31 to 34.
In response to a data input strobe signal ‘dinstb’ and starting addresses ‘add_start<1:4>’, the data input strobing unit 10 generates first, second, third, and fourth strobing addresses ‘add_str1<1:4>’, ‘add_str2<1:4>’, ‘add_str3<1:4>’, and ‘add_str4<1:4>’, and first to fourth precharging addresses ‘add_pcg<1:4>’.
In response to the first, second, third, and fourth strobing addresses ‘add_str1<1>’, ‘add_str2<1>’, ‘add_str3<1>’, and ‘add_str4<1>’, and the precharging address ‘add_pcg<1>’, the first data input sense amplifier 21 selectively amplifies the first, second, third, and fourth input data signals ‘din1’, ‘din2’, ‘din3’, and ‘din4’, and generates first amplified data signal ‘damp1’.
In response to the first, second, third, and fourth strobing addresses ‘add_str1<2>’, ‘add_str2<2>’, ‘add_str3<2>’, and ‘add_str4<2>’, and the precharging address ‘add_pcg<2>’, the second data input sense amplifier 22 selectively amplifies the first, second, third, and fourth input data signals ‘din1’, ‘din2’, ‘din3’, and ‘din4’, and generates second amplified data signal ‘damp2’.
In response to the first, second, third, and fourth strobing addresses ‘add_str1<3>’, ‘add_str2<3>’, ‘add_str3<3>’, and ‘add_str4<3>’, and the precharging address ‘add_pcg<3>’, the third data input sense amplifier 23 selectively amplifies the first, second, third, and fourth input data signals ‘din1’, ‘din2’, ‘din3’, and ‘din4’, and generates third amplified data signal ‘damp3’.
In response to the first, second, third, and fourth strobing addresses ‘add_str1<4>’, ‘add_str2<4>’, ‘add_str3<4>’, and ‘add_str4<4>’, and the precharging address ‘add_pcg<4>’, the fourth data input sense amplifier 24 selectively amplifies the first, second, third, and fourth input data signals ‘din1’, ‘din2’, ‘din3’, and ‘din4’, and generates fourth amplified data signal ‘damp4’.
The first to fourth data input drivers 31 to 34 are driven to transmit the first to fourth amplified data signals ‘damp1’ to ‘damp4’ and transmit them into the first to fourth global Input/Output lines GIO1 to GIO4, respectively.
In response to an enabled bit of the starting addresses ‘add_start<1:4>’ when the data input strobe signal ‘dinstb’ is enabled, the data input strobe unit 10 selectively enables one of the first, second, third, and fourth strobing addresses ‘add_str1<1:4>’, ‘add_str2<1:4>’, ‘add_str3<1:4>’, and ‘add_str4<1:4>’. For example, when the starting address ‘add_start<1>’ is enabled, the first strobing addresses ‘add_str1<1:4>’ are enabled. Then, the first to fourth data input sense amplifiers 21 to 24 amplify the first to fourth input data ‘din1’ to ‘din4’. When the starting addresses other than the starting address ‘add_start<1>’ are enabled, the strobing addresses other than the first strobing addresses ‘add_str1<1:4>’ are enabled. At this time, each of the first to fourth data input sense amplifiers 21 to 24 are allocated with a data combination different from a previous data combination. Each of the first to fourth data input sense amplifiers 21 to 24 amplifies an input data combination. Meanwhile, the precharching addresses ‘add_pcg_<1:4>’ are enabled with the data input strobe signal ‘dinstb’ being disabled, so that the first to fourth data input sense amplifiers 21 to 24 not to be activated.
The first to fourth data input driver 31 to 34 transmit the first to fourth amplified data ‘damp1’ to ‘damp4’, which are amplified by the first to fourth data input sense amplifiers 21 to 24, to the first to fourth global Input/Output lines GIO1 to GIO4, respectively. The first to fourth input data ‘din1’ to ‘din4’ are amplified and driven through the above-described process, and then transmitted to the first to fourth global Input/Output lines GIO1 to GIO4 in parallel.
It can be understood that the data input circuit having the above-described structure occupies a large area. For example, referring to FIG. 1, the number of output lines of the data input strobing unit 10 is 20. Each signal transmission line needs to have a predetermined insulated region in order to prevent noise between adjacent transmission lines. However, since the semiconductor memory apparatus includes a plurality of data input circuits, it can be understood that the data input circuits occupy a large area in the semiconductor memory apparatus.